In the DRAM, which is one of semiconductor memory devices, a memory cell is configured by one cell transistor and one storage capacitor, and thus, a higher storage capacity can be obtained as compared to other semiconductor memory devices. However, when the memory cell of the DRAM is miniaturized, an area on a semiconductor substrate which can be allocated to the storage capacitor becomes small. Thus, to secure a sufficient capacity value, it is required that the storage capacitor have a three-dimensional structure. As a storage capacitor having a three-dimensional structure, a stacked capacitor is well known (see Japanese Patent Applications Laid-open Nos. 2006-120832, 2000-77620, and 2003-264196).
FIG. 14 is a schematic cross-sectional view showing a conventional memory-cell structure having a stacked capacitor.
As shown in FIG. 14, the conventional DRAM is formed with two memory cells in one active region 11 divided by element isolation regions 12. That is, three diffusion regions 21 to 23 are formed in the active region 11. Above the diffusion regions 21 and 22 are adjacent to each other, and above the diffusion regions 21 and 23 are adjacent to each other. The gate electrodes 14 are formed via gate isolating films 13 on the semiconductor substrate. The gate electrodes 14 are word lines of the memory cell.
The three diffusion regions 21 to 23 are connected to cell contacts 31 to 33, respectively. Out of the cell contacts 31 to 33, the cell contact 31 connected to the center diffusion region 21 is connected to a bit line 15 via a bit contact 41 which passes through an interlayer insulating film 61. On the other hand, out of the cell contacts 31 to 33, the cell contacts 32 and 33 connected to the diffusion regions 22 and 23 respectively on both ends are connected to a storage capacitor 70 via capacitor contacts 52 and 53 which pass through the interlayer insulating film 61 and an interlayer insulating film 62.
The storage capacitor 70 is buried in a thick interlayer insulating film 63 and configured by a lower electrode 71, an upper electrode 72, and a capacitive insulating film 73. The lower electrode 71 is made of polycrystalline silicon and connected to the capacitor contacts 52 or 53. A plate potential is applied to the upper electrode 72. The capacitive insulating film 73 is placed between the lower electrode 71 and the upper electrode 72. The upper electrode 72 is covered by an interlayer insulating film 64.
When the memory cell having such structure is miniaturized, a distance D between the bit contact 41 and the capacitor contact 52 or 53 made of polycrystalline silicon becomes narrow, and thus, a processing margin decreases. Thus, the bit contact 41 and the capacitor contact 52 or 53 are short-circuited more easily.
To avoid shorting defects, it is necessary to reduce diameters of the capacitor contacts 52 and 53 located at the same height as that of the top surface of the bit contact 41. To satisfy this need, it is necessary to form a capacitor contact hole in a slanted manner such that the lower diameter is smaller than a diameter of an aperture. To form a slanted capacitor contact hole, a sufficient thickness of the interlayer insulating film 62 is necessary, for example, about 500 nm is necessary. As described above, to avoid shorting between the bit contact 41 and the capacitor contact 52 or 53, there is no other choice but to reduce the diameter (bottom diameter) at the bottom of the capacitor contact 52 or 53. As a result, a resistance value of the capacitor contacts 52 and 53 are increased.
Thus, the resistance value of the capacitor contact and a reliability thereof are in a trade-off relationship. Accordingly, it is conventionally difficult to prevent occurrence of shorting defects while decreasing the resistance value of the capacitive value.